This invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device with redundancy memory cells.
Recently, more and more semiconductor memory devices of high integration density have been developed in the art. High integration of the semiconductor devices causes a low yield in the fabrication of the semiconductor memory device. During the inspection process, all the memory cells of the respective semiconductor devices are tested for defects and if a few as one memory cell of a memory device is found to be defective, the memory device in question is usually considered to be defective. The number of defective memory cells increases as the number of memory cells incorporated in a semiconductor memory device increases. The technique of redundancy improves the yield of such semiconductor devices. This technique entails the incorporation of a redundancy memory cell array and exchange circuit, together with a main memory cell array, in the semiconductor memory device, and replaces the defective memory cells of the main memory cell array by the memory cells of the redundancy memory cell array in units of their row or column. Where any defective memory cells of the main memory cell array are to be replaced in units of their row, an exchange circuit causes the redundancy memory cell array to operate in place of the main memory cell array when a row address signal designates the row containing the defective memory cell of the main memory cell array. The exchange circuit has at least one programmable address detector for detecting a specified row address signal. As a method for programming the specified row address, a method which utilizes an EPROM, for example, is known, together with a method which utilizes fuse elements on a poly-Si structure, which are blown by a laser beam, etc.
FIG. 1 shows a programmable address detector which utilizes fuses. The address detector is supplied with a row address signal A of, for example, N bits, as well as a complementary replica A of row address signal A. In FIG. 1, A0, A1, . . . , AN represent the bits of row address signal A and AO, A1, . . . , AN represent the bits of complementary replica A. The address detector includes fuses 10-0, 10-1, . . . , 10-N and 11-0, 11-1, . . . , 11-N, p-channel MOS transistor 12 for a load, and n-channel MOS transistors 14-0, 14-1, . . . , 14-N and 15-0, 15-1, . . . , 15-N for drivers. The current path of MOS transistor 12 is connected at one end to a source potential terminal VCC (=5 V), and at the other end to an output line OUT. The output line OUT is connected to one of the spare word lines in the redundancy memory cell array. The gate of MOS transistor 12 is connected to a ground potential terminal VSS (=0 V) Fuses 10-0, 10-1, . . . , 10-N and 11-1, 11-2, . . . , 11-N are connected at one end to output line OUT, and at the other end to ground potential terminal VSS via the current paths of MOS transistors 14-0, 14-1, . . . , 14N and 15-0, 15-1, . . . , 15N. The gates of MOS transistors 14-0, 14-1, . . . , and 14N are connected to bits A0, Al, . . . , AN, and the gates of MOS transistors 15-0, 15-1, . . . , 15-N are connected to bits AO, A1, . . . , AN.
Before the programming or substitution step, fuses 10-1, 10-1, . . ., 10-N and 11-0, 11-1, . . . , 11-N all remain intact. When signals A and are supplied to the address detector, one of paired transistors 14-0 and 15-0, 14-1 and 15-1, . . ., 14-N and 15-N are selectively turned ON. The output line OUT is set at a low potential level by the turned-ON MOS transistors and corresponding fuses.
In the programming step, one of two fuses in each fuse pair 10-0 and 11-0, 10-1 and 11-1, . . . , 10-N and 11-N is selectively blown, so that the MOS transistors, which are turned ON in response to the specified signals A and A, are completely separated from output lie OUT. That is, output line OUT is normally set at a low-level potential and only when the row address signal designates a row corresponding to a defective memory cell in the main memory cell array, is it set at a high-level potential.
The spare word line, which is connected to output line OUT, is placed in a selected state when the potential of output line OUT is at high level, and is placed in a nonselected state when the potential of output OUT is at low level. The output signal of the address detector is used to keep the main memory cell array in an inoperative state during the time period in which the spare word line of the redundancy memory cell array is selected.
The memory device inspection process for the detection of any possible defects will now be explained in detail.
The memory devices are inspected for defects during the manufacturing process and also upon their completion. FIG. 2 shows a general flow of the inspection procedure conducted during the manufacture of the memory devices This inspection process begins at step 20, at which the semiconductor devices are formed on a single semiconductor wafer. At step 21, a series of tests is carried out on the respective memory devices, with regard to their operation functions, in particular, a test known as a "die sort test". In this test, measurement is made of the operation current, standby current, memory access time, stability against a fluctuation in a power supply voltage, and so on. If, at the end of the test, the memory device is found to be defective, it is rejected at step 22. If, on the other hand, the memory device is found to be defect-free, it is authorized and is subsequently packaged Only when a defective memory cell is found in the main memory cell array, is the defective cell subjected to a substitution process, at step 24. That is, the fuses in the address detector are selectively blown so that a specified address signal for designating the row containing the defective memory cell can be detected. Upon completion of this substitution process, the resultant memory device is again tested at step 25, to check whether or not it if functioning properly. If the memory device found to be functioning properly, it is accepted at step 23 and, if it is found to be defective, it is rejected at step 26.
This memory device does, however, have a the drawback in that unless the address detector is programmed, it is not possible to test whether or not the memory cells of the redundancy memory cell array are functioning properly. For this reason, the die sort test needs to be performed twice, once at step 21 and again, at step 25, hereby increasing the length of time necessary to perform inspection for defects. In the die sort test, needle-like probes are brought into contact with the bonding pads of the respective memory device. The bonding pads are normally formed of an aluminum film, and are thus liable to be damaged by the test probes. If any defective bonding occurs subsequently, as a result the bonding pads coming into contact with these probes, the yield in the fabrications of memory devices will be lowered. In view of this risk of damage, it is considered preferable to conduct a smaller number of such tests.
In particular, if the memory device is an EPROM type, the memory chip needs to be illuminated by ultraviolet radiation for a predetermined time period in order to erase the test data, thereby necessitating a greater amount of time for fabrication than is required for other memory devices. In the EPROM type memory device, furthermore, a predetermined test data pattern is generally written, during the die sort test, into the functioning memory cells. Upon completion of the memory device, subsequent to its being mold-packaged, the test data pattern is utilized once again, this time for the final inspection for defects. If the substitution process has been carried out with respect to some of the memory devices contained in the semiconductor wafer, it is then necessary to illuminate the semiconductor wafer by ultraviolet radiation, so that the retesting step can be performed on its memory devices. The test data pattern already written on the "accepted" memory device will be erased at the time this retesting step is performed. Therefore, it is necessary to once again write the test pattern data on the "accepted" memory device, prior to the packaging process.